Many high speed serial communication systems only transmit data over a communication media. In other words, these systems do not transmit clocks signals that may be used by a receiver to recover the data. Consequently, receivers for high speed serial communication systems often include a clock and data recovery circuit that produces a clock signal synchronized with the incoming data. The clock is then used to sample or recover the individual data bits.
In operation however, bandwidth limitations inherent in many communication media tend to create increasing levels of data distortion with increasing data rate and channel length. For example, band-limited channels tend to spread transmitted pulses. If the width of the spread pulse exceeds a symbol duration, overlap with neighboring pulses may occur, degrading the performance of the receiver. Therefore, typical high speed receivers may also include an adaptive equalizer, such as, for example, a decision feedback equalizer that removes or reduces channel induced inter-symbol interference.
In conventional receivers the extracted clock from the clock and data recovery circuit drives a retimer of the decision feedback equalizer to recover equalized data. However, variations in the delay along the processing path of the decision feedback equalizer can cause the clock and data recovery circuit to lose synchronization with the incoming data.